The present invention relates to a method and/or architecture for signal matching generally and, more particularly, to a method and/or architecture for signal matching in integrated circuits (ICs) and/or printed circuit boards (PCBs).
Referring to FIG. 1, a diagram of a conventional system 10 for signal line matching is shown. The system 10 generally comprises an output pin 12 and a number of input pins 14a-14n. Each of the input pins is connected to a common trace 16 by a number of traces 18a-18n. To compensate for various board layouts, the various traces 18a-18n may be implemented in a variety of manners such as a meander (or serpentine) and/or other manners. For example, the trace 18a is farther from the output pin 12 than, for example, the trace 18d. For the entire distance between the output pin 12 to the input pin 14d to be equal to the other traces 18a-18n, the trace 18d must be made longer, by adding additional trace length (i.e., the meander sections). The meander sections of the traces 18a-18n provide a generic distance from the output pin 12 to each of the input pins 14a-14n, respectively.
Another conventional approach for signal line matching is disclosed by U.S. Pat. No. 4,812,684. The conventional approach of U.S. Pat. No. 4,812,684 discloses a scheme implementing a number of intermediate buffers. However, such intermediate buffers add considerable additional circuit design.
Another conventional approach for signal line matching is disclosed by U.S. Pat. No. 5,109,168. The conventional approach of U.S. Pat. No. 5,109,168 discloses a number of signal lines that are split architecturally. Since the signals turn 90 degrees and tend to form a loop, increased inductance can be experienced. Increased inductance can limit high frequency operation and can create ground bounce according to the equation L*di/dt, where i is current and t is time. Since low inductance is important for high frequency applications, the split architecture approach is not ideal.
Another conventional approach for signal line matching is disclosed by U.S. Pat. No. 5,410,491. The conventional approach of U.S. Pat. No. 5,410,491 implements complicated algorithms to balance various branches. Such an implementation increases complexity and associated errors. Additionally, U.S. Pat. No. 5,410,491 is similar to U.S. Pat. No. 5,109,168 and requires additional circuitry.
Conventional methods of matching signal lines can be performed by meandering tracks to match physical lengths of signal lines or by adding stubs to match capacitances of variable length signal lines. The meanders are implemented to keep distance from the output pin 12 to each of the input pins 14a-14n identical. The conventional meanders and/or addition of stubs is time consuming, untidy and is not methodical.
It is therefore desirable to provide a signal matching device that may be implemented with low inductance, which may enable high frequency chips, such as clock chips with tight skew parameters and/or specifications to be implemented properly. Additionally, low inductance may also reduce setting times of the output signals.
The present invention concerns an apparatus comprising an output connected to a plurality of inputs through a tree of connections. Each of one or more branches of the tree may be equidistant between the output and each of the plurality of inputs.
The objects, features and advantages of the present invention include providing a method and/or architecture for signal matching in integrated circuits (ICs) and/or printed circuit boards (PCBs) that may (i) implement meanders to keep all signal paths equidistant, (ii) match signal lines to any number of inputs from a single output, (iii) implement splits that travel an equal distance before they split again to guarantee equidistant lines, and/or (iv) implement all lines in a methodical manner, ensuring clarity, ease of construction and saving production time.